Flexible Self-Aligned Double-Gate IGZO TFT
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Abstract
In this letter, flexible double-gate (DG) thin-film transistors (TFTs) based on InGaZnO4 and fabricated on free standing plastic foil, using self-alignment (SA) are presented. The usage of transparent indium-tin-oxide instead of opaque metals enables SA of source-, drain-, and top-gate contacts. Hence, all layers, which can cause parasitic capacitances, are structured by SA. Compared with bottom-gate reference TFTs fabricated on the same substrate, DG TFTs exhibit a by 68% increased transconductance and a subthreshold swing as low as 109 mV/dec decade (-37%). The clockwise hysteresis of the DG TFTs is as small as 5 mV. Because of SA, the source/drain to gate overlaps are as small as ≃ 1 μm leading to parasitic overlap capacitances of 5.5 fF μm-1. Therefore a transit frequency of 5.6 MHz is measured on 7.5 μm long transistors. In addition, the flexible devices stay fully operational when bent to a tensile radius of 6 mm.
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<record><TEI><teiHeader><fileDesc><titleStmt><title xml:lang="en" level="a">Flexible Self-Aligned Double-Gate IGZO TFT</title><author><name sortKey="M Nzenrieder, Niko" uniqKey="M Nzenrieder N">Niko M Nzenrieder</name><affiliation wicri:level="1"><inist:fA14 i1="01"><s1>Institute for Electronics, Swiss Federal Institute of Technology Zürich</s1><s2>Zürich 8092</s2><s3>CHE</s3><sZ>1 aut.</sZ><sZ>2 aut.</sZ><sZ>3 aut.</sZ><sZ>4 aut.</sZ><sZ>5 aut.</sZ><sZ>6 aut.</sZ><sZ>7 aut.</sZ><sZ>8 aut.</sZ></inist:fA14><country>Suisse</country><wicri:noRegion>Zürich 8092</wicri:noRegion></affiliation></author><author><name sortKey="Voser, Pascal" uniqKey="Voser P">Pascal Voser</name><affiliation wicri:level="1"><inist:fA14 i1="01"><s1>Institute for Electronics, Swiss Federal Institute of Technology Zürich</s1><s2>Zürich 8092</s2><s3>CHE</s3><sZ>1 aut.</sZ><sZ>2 aut.</sZ><sZ>3 aut.</sZ><sZ>4 aut.</sZ><sZ>5 aut.</sZ><sZ>6 aut.</sZ><sZ>7 aut.</sZ><sZ>8 aut.</sZ></inist:fA14><country>Suisse</country><wicri:noRegion>Zürich 8092</wicri:noRegion></affiliation></author><author><name sortKey="Petti, Luisa" uniqKey="Petti L">Luisa Petti</name><affiliation wicri:level="1"><inist:fA14 i1="01"><s1>Institute for Electronics, Swiss Federal Institute of Technology Zürich</s1><s2>Zürich 8092</s2><s3>CHE</s3><sZ>1 aut.</sZ><sZ>2 aut.</sZ><sZ>3 aut.</sZ><sZ>4 aut.</sZ><sZ>5 aut.</sZ><sZ>6 aut.</sZ><sZ>7 aut.</sZ><sZ>8 aut.</sZ></inist:fA14><country>Suisse</country><wicri:noRegion>Zürich 8092</wicri:noRegion></affiliation></author><author><name sortKey="Zysset, Christoph" uniqKey="Zysset C">Christoph Zysset</name><affiliation wicri:level="1"><inist:fA14 i1="01"><s1>Institute for Electronics, Swiss Federal Institute of Technology Zürich</s1><s2>Zürich 8092</s2><s3>CHE</s3><sZ>1 aut.</sZ><sZ>2 aut.</sZ><sZ>3 aut.</sZ><sZ>4 aut.</sZ><sZ>5 aut.</sZ><sZ>6 aut.</sZ><sZ>7 aut.</sZ><sZ>8 aut.</sZ></inist:fA14><country>Suisse</country><wicri:noRegion>Zürich 8092</wicri:noRegion></affiliation></author><author><name sortKey="B The, Lars" uniqKey="B The L">Lars B The</name><affiliation wicri:level="1"><inist:fA14 i1="01"><s1>Institute for Electronics, Swiss Federal Institute of Technology Zürich</s1><s2>Zürich 8092</s2><s3>CHE</s3><sZ>1 aut.</sZ><sZ>2 aut.</sZ><sZ>3 aut.</sZ><sZ>4 aut.</sZ><sZ>5 aut.</sZ><sZ>6 aut.</sZ><sZ>7 aut.</sZ><sZ>8 aut.</sZ></inist:fA14><country>Suisse</country><wicri:noRegion>Zürich 8092</wicri:noRegion></affiliation></author><author><name sortKey="Vogt, Christian" uniqKey="Vogt C">Christian Vogt</name><affiliation wicri:level="1"><inist:fA14 i1="01"><s1>Institute for Electronics, Swiss Federal Institute of Technology Zürich</s1><s2>Zürich 8092</s2><s3>CHE</s3><sZ>1 aut.</sZ><sZ>2 aut.</sZ><sZ>3 aut.</sZ><sZ>4 aut.</sZ><sZ>5 aut.</sZ><sZ>6 aut.</sZ><sZ>7 aut.</sZ><sZ>8 aut.</sZ></inist:fA14><country>Suisse</country><wicri:noRegion>Zürich 8092</wicri:noRegion></affiliation></author><author><name sortKey="Salvatore, Giovanni A" uniqKey="Salvatore G">Giovanni A. Salvatore</name><affiliation wicri:level="1"><inist:fA14 i1="01"><s1>Institute for Electronics, Swiss Federal Institute of Technology Zürich</s1><s2>Zürich 8092</s2><s3>CHE</s3><sZ>1 aut.</sZ><sZ>2 aut.</sZ><sZ>3 aut.</sZ><sZ>4 aut.</sZ><sZ>5 aut.</sZ><sZ>6 aut.</sZ><sZ>7 aut.</sZ><sZ>8 aut.</sZ></inist:fA14><country>Suisse</country><wicri:noRegion>Zürich 8092</wicri:noRegion></affiliation></author><author><name sortKey="Troster, Gerhard" uniqKey="Troster G">Gerhard Tröster</name><affiliation wicri:level="1"><inist:fA14 i1="01"><s1>Institute for Electronics, Swiss Federal Institute of Technology Zürich</s1><s2>Zürich 8092</s2><s3>CHE</s3><sZ>1 aut.</sZ><sZ>2 aut.</sZ><sZ>3 aut.</sZ><sZ>4 aut.</sZ><sZ>5 aut.</sZ><sZ>6 aut.</sZ><sZ>7 aut.</sZ><sZ>8 aut.</sZ></inist:fA14><country>Suisse</country><wicri:noRegion>Zürich 8092</wicri:noRegion></affiliation></author></titleStmt><publicationStmt><idno type="inist">14-0051107</idno><date when="2014">2014</date><idno type="stanalyst">PASCAL 14-0051107 INIST</idno><idno type="RBID">Pascal:14-0051107</idno><idno type="wicri:Area/Main/Corpus">000155</idno><idno type="wicri:Area/Main/Repository">000124</idno></publicationStmt><seriesStmt><idno type="ISSN">0741-3106</idno><title level="j" type="abbreviated">IEEE electron device lett.</title><title level="j" type="main">IEEE electron device letters</title></seriesStmt></fileDesc><profileDesc><textClass><keywords scheme="KwdEn" xml:lang="en"><term>Doped materials</term><term>Flexible structure</term><term>Gallium oxide</term><term>Indium oxide</term><term>Plastics</term><term>Self aligned technology</term><term>Spurious capacity</term><term>Thin film transistor</term><term>Tin addition</term><term>Top contact configuration</term><term>Transconductance</term><term>Zinc oxide</term></keywords><keywords scheme="Pascal" xml:lang="fr"><term>Technologie autoalignée</term><term>Transistor couche mince</term><term>Addition étain</term><term>Capacité parasite</term><term>Transconductance</term><term>Matière plastique</term><term>Oxyde d'indium</term><term>Structure flexible</term><term>Oxyde de gallium</term><term>Oxyde de zinc</term><term>Matériau dopé</term><term>ITO</term><term>Configuration top contact</term></keywords><keywords scheme="Wicri" type="concept" xml:lang="fr"><term>Matière plastique</term></keywords></textClass></profileDesc></teiHeader><front><div type="abstract" xml:lang="en">In this letter, flexible double-gate (DG) thin-film transistors (TFTs) based on InGaZnO<sub>4</sub> and fabricated on free standing plastic foil, using self-alignment (SA) are presented. The usage of transparent indium-tin-oxide instead of opaque metals enables SA of source-, drain-, and top-gate contacts. Hence, all layers, which can cause parasitic capacitances, are structured by SA. Compared with bottom-gate reference TFTs fabricated on the same substrate, DG TFTs exhibit a by 68% increased transconductance and a subthreshold swing as low as 109 mV/dec decade (-37%). The clockwise hysteresis of the DG TFTs is as small as 5 mV. Because of SA, the source/drain to gate overlaps are as small as ≃ 1 μm leading to parasitic overlap capacitances of 5.5 fF μm<sup>-1</sup>. Therefore a transit frequency of 5.6 MHz is measured on 7.5 μm long transistors. In addition, the flexible devices stay fully operational when bent to a tensile radius of 6 mm.</div></front></TEI><inist><standard h6="B"><pA><fA01 i1="01" i2="1"><s0>0741-3106</s0></fA01><fA02 i1="01"><s0>EDLEDZ</s0></fA02><fA03 i2="1"><s0>IEEE electron device lett.</s0></fA03><fA05><s2>35</s2></fA05><fA06><s2>1</s2></fA06><fA08 i1="01" i2="1" l="ENG"><s1>Flexible Self-Aligned Double-Gate IGZO TFT</s1></fA08><fA11 i1="01" i2="1"><s1>MÜNZENRIEDER (Niko)</s1></fA11><fA11 i1="02" i2="1"><s1>VOSER (Pascal)</s1></fA11><fA11 i1="03" i2="1"><s1>PETTI (Luisa)</s1></fA11><fA11 i1="04" i2="1"><s1>ZYSSET (Christoph)</s1></fA11><fA11 i1="05" i2="1"><s1>BÜTHE (Lars)</s1></fA11><fA11 i1="06" i2="1"><s1>VOGT (Christian)</s1></fA11><fA11 i1="07" i2="1"><s1>SALVATORE (Giovanni A.)</s1></fA11><fA11 i1="08" i2="1"><s1>TRÖSTER (Gerhard)</s1></fA11><fA14 i1="01"><s1>Institute for Electronics, Swiss Federal Institute of Technology Zürich</s1><s2>Zürich 8092</s2><s3>CHE</s3><sZ>1 aut.</sZ><sZ>2 aut.</sZ><sZ>3 aut.</sZ><sZ>4 aut.</sZ><sZ>5 aut.</sZ><sZ>6 aut.</sZ><sZ>7 aut.</sZ><sZ>8 aut.</sZ></fA14><fA20><s1>69-71</s1></fA20><fA21><s1>2014</s1></fA21><fA23 i1="01"><s0>ENG</s0></fA23><fA43 i1="01"><s1>INIST</s1><s2>222V</s2><s5>354000501676680230</s5></fA43><fA44><s0>0000</s0><s1>© 2014 INIST-CNRS. All rights reserved.</s1></fA44><fA45><s0>14 ref.</s0></fA45><fA47 i1="01" i2="1"><s0>14-0051107</s0></fA47><fA60><s1>P</s1></fA60><fA61><s0>A</s0></fA61><fA64 i1="01" i2="1"><s0>IEEE electron device letters</s0></fA64><fA66 i1="01"><s0>USA</s0></fA66><fC01 i1="01" l="ENG"><s0>In this letter, flexible double-gate (DG) thin-film transistors (TFTs) based on InGaZnO<sub>4</sub> and fabricated on free standing plastic foil, using self-alignment (SA) are presented. The usage of transparent indium-tin-oxide instead of opaque metals enables SA of source-, drain-, and top-gate contacts. Hence, all layers, which can cause parasitic capacitances, are structured by SA. Compared with bottom-gate reference TFTs fabricated on the same substrate, DG TFTs exhibit a by 68% increased transconductance and a subthreshold swing as low as 109 mV/dec decade (-37%). The clockwise hysteresis of the DG TFTs is as small as 5 mV. Because of SA, the source/drain to gate overlaps are as small as ≃ 1 μm leading to parasitic overlap capacitances of 5.5 fF μm<sup>-1</sup>. Therefore a transit frequency of 5.6 MHz is measured on 7.5 μm long transistors. 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